A feature useful to many systems is the reduction or virtual elimination of power consumption when the device is not in use, is partially functioning, or is being prepared for a fast transition to any functioning condition. Apart from the full power down condition (system off), other reduced-power modes are often explicitly defined. The system configuration in these modes and the transitions between different functioning modes may make it necessary to devise and design specific circuitry to manage these conditions efficiently and reliably.
When the system clock is generated by the device under power control, a correct functioning of the device during transitions between two different power saving modes of the device and the resuming out of these modes should be ensured also when internal PLLs/DLLs have not yet locked to their reference signal. Techniques for reducing static power dissipation in monolithic electronics devices through the definition of power islands, as parts of the integrated systems submitted to distinct power domains (or islands of functional circuitries), is known in the art. See, e.g., [2], [3].
The distinct power domains may be independently supplied, thereby changing the supply values depending on the performance standards of the circuitry in the power island. A selective power-off of the different supply islands may also be contemplated and implemented, see, e.g., [3], for reducing static power consumption whenever circuits included in the power island are not in use.
The cited prior documents do not suggest how to manage the clock generated inside a monolithic device implementing a power saving mode, when the clock is also used outside the device and when specific requirements need to be satisfied, such as the correct generation of the clock during and after all transitions from the power saving modes to those modes in which the clock is used and propagated.